In some circumstances, it is desirable to provide physical security for electronic hardware. For example, it may be desirable to protect data stored in a memory or processing device. Such data may include cryptographic keys or any other sensitive information. It is therefore known to package such hardware in a coating, which in some cases is arranged such that, if the enclosing material is tampered with, data is blanked, or otherwise made unusable.
One known technique, as illustrated in FIG. 1A, is to wrap hardware in a tamper responsive mesh 102 (e.g. products from W.L. Gore and Associates) which consists of an electrical matrix that can detect an attempt at penetration due to a change in resistance. In the example of FIG. 1A, a security module 100 housing a Stacked Chip ‘System on Chip’ package 101 is shown, comprising a Dynamic memory (DRAM) chip 104 mounted on top of an application-specific integrated circuit (ASIC) 106. The stacked chips 104, 106, are in turn mounted on an intermediate substrate 108, which in this example includes Vertical Interconnect Accesses (vias) 110 (only two of which are labelled for reasons of clarity), allowing data and power to pass through the intermediate substrate 108. These elements are then mounted, via a number of solder ball bonds 112, on a Printed Circuit Board (PCB) 114. As will be appreciated by the skilled person, the PCB 114 will also comprise a connection, which passes through the tamper responsive mesh 102. For additional security, the whole package is also surrounded by encapsulating resin 116 to form the security module 100.
The skilled person will also be familiar with methods for providing such protection at chip level, as is illustrated schematically in FIG. 1B. As will be familiar to the skilled person, a chip or ‘die’ 150 is usually built up in layers on a substrate 152, which is often (but not always) made of silicon. Functional components are either added to or formed from the material of the substrate 152 in a lithographic process to form a portion of the die 150 termed herein a ‘functional region’ 154, and which is designed to allow the die 150 to perform its intended function. As will be familiar to the skilled person, the functionality of the die 150 is defined by forming layers (which are layers within of the function region 154) of treated silicon, deposited material or the like. One known anti-tamper option is to include upper metal layer(s) in the die 150 to provide a tamper shield 156 (active and/or passive) to mitigate against such attacks. For example, a tamper shield 156 may comprise one or more metal track(s) arranged in coil (often a square or rectangular coil), or as a series of parallel tracks, or the like. However, such an approach has an important residual vulnerability—an attack can be made from the base of the die 150 through the substrate 152.
To address this, the skilled person may wrap a die (and/or the package containing the die) with a separate mesh such as the Gore mesh described above but this adds complexity and cost to the manufacturing process.